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MyHDL Resources

A curated list of tutorials, projects, and third-party tools to be used in conjunction with the open source MyHDL hardware design language.

You can add your own stuff to this! Please read the contribution guidelines to see how.

MyHDL Resources

Tutorials

MyHDL Reference Manual - The go-to document for the MyHDL language.
Hello World - Shows how a demonstrator design that was originally coded in VHDL can be done in MyHDL.
Flip-Flops and Latches - Explains basic MyHDL usage with small, widely-known circuits.
Bitonic Sort - Presents possibilities for describing hardware structures in MyHDL, focusing on a classic sorting function.
PygMyHDL Tutorials - A sequence of Jupyter notebooks that use PygMyHDL (MyHDL + simple wrapper) to describe, compile, download and run several digital logic circuits on the low-cost iCEstick FPGA board.
MyHDL Cheat Sheet - An abstract for the MyHDL language keywords.
modbv Example - An example of the use of the modbv type introduced in MyHDL 0.8.
LED Strober - Shows a complete implementation of a circuit that recreates the strobe effect of the Knightrider Trans Am.
Audio Echo - Describes how to produce an echo on a stream of digitized audio samples. A companion article adds further details concerning the actual implementation with an AIC23 codec chip.
Simple Co-Simulation Example - This code snippet uses three modules to present the absolute minimum for a co-simulation of Verilog code and MyHDL code.
OO Design in MyHDL - An example of using object-oriented design principles with MyHDL.
FPGA Designs With MyHDL - A reimagining of these VHDL/Verilog designs in MyHDL.

Projects

Johnson Counter - Presents the design of a reversible, glitch-free, 4 bit Johnson counter.
Stopwatch - Describes the design of a simple stopwatch.
Pulse Width Modlator - A simple PWM along with several test setups.
Cordic-Based Sine Computer - Presents the design of a sine and cosine computer.
Hardware Sorters - A Jupyter notebook describing, simulating, and comparing two hardware-based circuits for sorting a list of numbers.
Exploring Random Number Generators with MyHDL - Illustrates the advantages of using MyHDL and Python in designing and testing a random number generator (RNG).
Simple IIR Filter - A simple infinite impulse response (IIR) Lowpass Direct Form I Filter.
Simple FIR Filter - A simple finite impulse response (FIR) filter.
Recursive FFT - Fast Fourier Transform in MyHDL and translatable to Verilog or VHDL for hardware implementation. See this for additional explanation.
AIC23b Audio Codec Interface - An interface for configuring the AIC23 codec and sampling/generating audio signals.
myhdl_lib - A MyHDL library of generic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc. All components are tested with Icarus Verilog simulator.
rhea - A collection of HDL cores along with a small set of utilities to augment the MyHDL types and functions as well as FPGA build automation tools.
KalmanFilter - A simple, low-resource usage Kalman Filter using shared resources.
myhdl_simple_uart - Implements a simple UART in MyHDL and generates the VHDL files. It has been tested in a DE2-115 board.
Spiking Neuron - Implements a spiking neuron based on the model described in Izhikevich, E. M., "Simple Model of Spiking Neurons" IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 6, NOVEMBER 2003.
Algol RISCV CPU core - A CPU core that implements the RISC-V RV32IM Instruction Set.
alt.hdl - A collection of complete and partial design examples built using MyHDL, bsv, and chisel.
PyMIPS - A formal implementation of a MIPS processor as described in Computer Organization and Design by Hennessy/Patterson.
RISC-V - A RISC-V implementation and tools.
MyBlaze - a synthesizable clone of the MicroBlaze Soft Processor.
Skip-Gram Model for Word Embeddings - Implementation in MyHDL of a neural network using the skip-gram model for natural language processing.
VGA Bouncing Ball - A circuit that displays a bouncing ball on a VGA monitor.
Whitebox - A cross between a smartphone and a software defined radio with the DSP section described using MyHDL.
HDL-deflate - Implementation of deflate (de)compress RFC 1950/1951.
Kea - Some useful HDL blocks, mainly an AXI Lite register subsystem, along with supporting AXI Lite and Stream interfaces and associated BFMs.
Verilog PCIexpressComponents - A collection of PCI express related components including a full MyHDL & Verilog testbench with intelligent bus cosimulation endpoints.
myBFSK - Example of receiver for continuous phase binary frequency shift keying signals with modulation index less then 1.0 written in myHDL.
CS3339-MIPS32 - This project simulates a MIPS-like 5 stage pipeline through co-simulation between Python and Icarus Verilog. The machine is implemented with a 32-bit architecture through the myHDL library.
1pCPU - A small 8bit CPU written with MyHDL in a Jupyter notebook.
jupyosys - MyHDL extensions to support direct RTL generation and synthesis through yosys

Third-Party Tools

myhdlpeek - A Python package that lets you monitor and display signal waveforms from your MyHDL digital design in a Jupyter notebook.
PygMyHDL - A Python package that places a thin-wrapper around MyHDL to make it a bit easier for beginners to get started.
Ovenbird - A tool for merging the MyHDL workflow with Vivado.
MyHDLXilinxUnisimLib - MyHldXilinxUnisimLib lets you use Xilinx Unisim components within a MyHDL project.
Synthia - A simple IDE that uses MyHDL, yosys, and arachne-pnr to target the ICEStick.
pyFDA - A GUI-based tool for analysing and designing discrete time filters. May be using MyHDL to generate HDL implementations of the filters.
Veriutils - A collection of utilities for verification of HDL designs created using MyHDL.
MyHDL Numeric - MyHDL-numeric is an enhancement of the MyHDL package which provides support for multiple VHDL entities (MEP110) and fixed-point numbers (MEP111).
myhdl2dot - Generates a flowgraph for a MyHDL design using graphviz.
VSCode MyHDLTools - Provides some helpful code generators for using MyHDL for Verilog Cosimulation.
HDL playground - Jupyter notebook environment for MyHDL/VHDL/Verilog synthesis from the Browser, based on the jupyosys project (Docker container or Google Binder)

License

To the extent possible under law, Dave Vandenbout has waived all copyright and related or neighboring rights to this work.