Awesome
Must-have verilog systemverilog modules
Originally published as part of https://github.com/pConst/basic_verilog
by Konstantin Pavlov, pavlovconst@gmail.com
Hi! This is a collection of Verilog SystemVerilog synthesizable modules.
All the code is highly reusable across typical FPGA projects and mainstream FPGA vendors.
Please feel free to make pull requests or contact me in case you spot any code issues.
Also, give me a pleasure, tell me if the code has got succesfully implemented in your hobby, scientific or industrial projects!
Licensing
The code is licensed under CC BY-SA 4_0
That means, that you can remix, transform, and build upon the material for any purpose, even commercially.
However, YOU MUST provide the name of the creator and distribute your contributions under the same license as the original.
Contents description
For your convinience I`ve tagged some sources by their "difficulty":
:green_circle: - for the most basic tasks
:red_circle: - for advanced or special purpose routines
If you are a beginner in HW design - you may want to start exploring :green_circle: code first.
Almost every source file in the repository contains detailed description and instantiation template!
| DIRECTORY | DESCRIPTION | |
|---|---|---|
| Advanced Synthesis Cookbook/ | useful code from Altera's cookbook | |
| KCPSM6_Release9_30Sept14/ | Xilinx's Picoblaze soft processor sources | |
| :red_circle: | XilinxBoardStore_with_Alveo_cards_support | board definitions for Xilinx Alveo accelerator cards |
| pacoblaze-2.2/ | version of Picoblaze adapted for Altera devices | |
| avalon_mm_master_templates/ | Avalon-MM component templates from Altera | |
| axi_master_slave_templates/ | AXI componet templates generated by Vivado | |
| benchmark_projects/ | benchmarking various IDEs to compile exact same Verilog project | |
| dual_port_ram_templates/ | Block RAM templates | |
| example_projects/ | FPGA project boilerplates and examples | |
| gitignores/ | gitignore files for FPGA projects | |
| scripts/ | useful TCL, batch and shell scripts | |
| :red_circle: | scripts_for_intel_hls/ | useful scripts for compiling for Intel HLS |
| :red_circle: | scripts_for_xilinx_hls/ | useful scripts for compiling for Xilinx HLS |
| xpm | Xilinx parametrizable macros sources |
| FILE | DESCRIPTION | |
|---|---|---|
| adder_tree.sv | adding multiple values together in parallel | |
| axi4l_logger.sv | sniffs all AXI transactions and stores address and data to fifo | |
| :green_circle: | bin2gray.sv | combinational Gray code to binary converter |
| bin2pos.sv | converts binary coded value to positional (one-hot) code | |
| cdc_data.sv | standard two-stage data synchronizer | |
| cdc_strobe.sv | clock crossing synchronizer for one-cycle strobes | |
| :green_circle: | clk_divider.sv | wide reference clock divider |
| clogb2.svh | calculates counter/address width based on specified vector/RAM depth | |
| :green_circle: | debounce.v | two-cycle debounce for input buttons |
| :green_circle: | delay.sv | useful module to make static delays or to synchronize across clock domains |
| delayed_event.sv | generates delayed pulse one clock width | |
| dynamic_delay.sv | dynamic delay for arbitrary input signal | |
| :green_circle: | edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge |
| encoder.v | digital encoder input logic module | |
| :red_circle: | fast_counter.sv | synthetic counter |
| fifo_combiner.sv | accumulates data words from multiple FIFOs to a single output FIFO | |
| fifo_operator.sv | performs custom operation on data words from multiple FIFOs and stores result to a single output FIFO | |
| :red_circle: | fifo_single_clock_ram_*.sv | single-clock FIFO buffer (queue) implementation |
| :red_circle: | fifo_single_clock_reg_*.sv | single-clock FIFO buffer (queue) implementation |
| :green_circle: | gray2bin.sv | combinational binary to Gray code converter |
| :red_circle: | gray_functions.vh | Gray code parametrizable converter functions |
| :green_circle: | hex2ascii.sv | converts 4-bit binary nibble to 8-bit human-readable ASCII char |
| leave_one_hot.sv | combinational module that leaves only lowest hot bit | |
| lifo.sv | single-clock LIFO buffer (stack) implementation | |
| main_tb.sv | basic testbench template | |
| moving_average.sv | Simple moving average implementation | |
| pack_unpack_array.v | macros for packing and unpacking 2D and 3D vectors in Verilog-2001 | |
| pattern_detect.sv | detects data pattern specified | |
| pdm_modulator.sv | pulse density modulation generator module | |
| pos2bin.sv | converts positional (one-hot) value to binary representation | |
| prbs_gen_chk.sv | PRBS pattern generator or checker | |
| preview_fifo.sv | FIFO with an ability to be read 0, 1 or 2 words at once | |
| priority_enc.sv | combinational priority_encoder | |
| pulse_gen.sv | generates pulses with given width and delay | |
| pulse_stretch.sv | configurable pulse stretcher/extender module | |
| pwm_modulator.sv | pulse width modulation generator | |
| :red_circle: | read_ahead_buf.sv | substitutes fifo read port and performs fifo data update at the same clock cycle |
| reset_set.sv | SR trigger variant w/o metastable state, set dominates here | |
| reset_set_comb.sv | synchronous SR trigger, but has a combinational output | |
| reverse_bytes.sv | reverses bytes order within multi-byte array | |
| reverse_dimensions.sv | reverses dimension order in SystemVerilog 2D vector | |
| reverse_vector.sv | reverses signal order within multi-bit bus | |
| round_robin_enc.sv | round robin combinational encoder | |
| round_robin_performance_enc.sv | performance improved round robin encoder | |
| set_reset.sv | SR trigger variant w/o metastable state, reset dominates here | |
| set_reset_comb.sv | synchronous SR trigger, but has a combinational output | |
| sim_clk_gen.sv | testbench clock generator | |
| :red_circle: | soft_latch.sv | combinational data hold circuit |
| spi_master.sv | universal spi master module | |
| :red_circle: | true_dual_port_write_first_2_clock_ram.sv | double port RAM/ROM module |
| :red_circle: | true_single_port_write_first_ram.sv | single port RAM/ROM module |
| uart_debug_printer.sv | debug data printer to UART terminal | |
| :green_circle: | uart_rx.sv | straightforward yet simple UART receiver |
| uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs | |
| :green_circle: | uart_tx.sv | straightforward yet simple UART transmitter |
| uart_tx_shifter.sv | UART-like transmitter shifter for simple synchronous messaging inside the FPGA or between FPGAs |
Also added testbenches for selected modules.