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OpenHW Group CORE-V CVE2 RISC-V IP

CVE2 is a class of 2-stage pipeline OpenHW Group cores. Currently, the only core in this class is the CV32E20. CV32E20 is a fork of the Ibex core. Differently to Ibex, cv32e2 will target low cost as originally intended in the Zero-riscy project. The core will be made compatible with the OpenHW Group OBI protocol, it will use the same sleep unit of CV32E4 family, and it will achieve TRL5 with the industrial-level verification core-v-verif.

CV32E20 RISC-V Core

CV32E20 is a production-quality open source source 32-bit RISC-V CPU core written in SystemVerilog. The CPU core is heavily parametrizable and well-suited for embedded control applications. CV32E20 is being extensively verified and has seen multiple tape-outs. CV32E20 supports the Integer (I) or Embedded (E), Integer Multiplication and Division (M), and Compressed (C) extensions.

The block diagram below shows the small parametrization with a 2-stage pipeline.

<p align="center"><img src="doc/03_reference/images/blockdiagram.svg" width="650"></p>

CV32E20 was initially developed as part of the PULP platform under the name "Zero-riscy", and has been contributed to lowRISC who maintains it and develops it further. It was further adopted by the OpenHW Group to work towards an improved industrialization

Verification

The verification environment for the CVE2 is not in this Repository. There is a small, simple testbench here which is useful for experimentation only and should not be used to validate any changes to the RTL prior to pushing to the master branch of this repo.

The verification environment for this core as well as other cores in the OpenHW Group CORE-V family is at the core-v-verif repository on GitHub.

The Makefiles supported in the core-v-verif project automatically clone the appropriate version of the cve2 RTL sources.

Changelog

A changelog is generated automatically in the documentation from the individual pull requests. In order to enable automatic changelog generation within the documentation, the committer is required to label each pull request that touches any file in 'rtl' (or any of its subdirectories) with Component:RTL and label each pull request that touches any file in 'docs' (or any of its subdirectories) with Component:Doc. Pull requests taht are not labeled or labeled with ignore-for-release are ignored for the changelog generation.

Only the person who actually performs the merge can add these labels (you need committer rights). The changelog flow only works if at most 1 label is applied and therefore pull requests that touch both RTL and documentation files in the same pull request are not allowed.

Configuration

CV32E20 offers several configuration parameters to meet the needs of various application scenarios. The options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features. The table below indicates performance, area, and verification status for a few selected configurations. These are configurations on which lowRISC is focusing for performance evaluation and design verification (see supported configs).

Config"micro""small"
FeaturesRV32ECRV32IMC, 3 cycle mult
Performance (CoreMark/MHz)0.9042.47
Area - Yosys (kGE)16.8526.60
Area - Commercial (estimated kGE)~15~24
Verification status

Notes:

Documentation (to be updated)

The CVE2 documentation can be read online at ReadTheDocs. It is also contained in the doc folder of this repository.

Examples

The CVE2 repository includes Simple System. This is an intentionally simple integration of CV32E20 with a basic system that targets simulation. It is intended to provide an easy way to get bare metal binaries running on CV32E20 in simulation.

Contributing

We highly appreciate community contributions. We are currently using the lowRISC contribution guide. To ease our work of reviewing your contributions, please:

For more details on how this is implemented, have a look at this page.

When contributing SystemVerilog source code, please try to be consistent and adhere to the lowRISC Verilog coding style guide.

To get started, please check out the "Good First Issue" list.

The RTL code has been formatted with "Verible" v0.0-1149-g7eae750. Run ./util/format-verible to format all the files.

Issues and Troubleshooting

If you find any problems or issues with CVE2 or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.

License

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).

Credits

Many people have contributed to CVE2 and its predecessor projects through the years. Please have a look at the credits file and the commit history for more information.

References

Schiavone, Pasquale Davide, et al. "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications." 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017)