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verilog-ext.el - SystemVerilog Extensions for Emacs

This package provides useful extensions on top of verilog-mode and verilog-ts-mode.

• Tree-sitter verilog-ts-mode support
• Project management
• Improve syntax highlighting
• Find definitions and references
• Auto-completion with dot and scope completion
• Hierarchy extraction and navigation
• LSP configuration for lsp-bridge, lsp-mode,eglot and lspce
• Support for many linters via flycheck
• Beautify modules and instances
• Code navigation functions for RTL and Verification environments
• Extended collection of templates via yasnippet and hydra
• Code formatter via apheleia
• Compilation with colored errors/warnings and jump to file/line
• Improve imenu entries: detect instances, classes and methods
• Enhanced support for which-func
• Code folding via hideshow
• Highlight and align typedefs
• Auto-configure time-stamp
• Auto-convert block end comments to names
• Port connection utilities

Requirements

• Emacs 29.1+
• Latest verilog-mode version
• Feature-specific binaries

Tree-sitter is optional but recommended and only required if using verilog-ts-mode for some of the features above.

For more info, see the wiki.

Installation

MELPA

verilog-ext is available on MELPA.

straight.el

To install it via straight with use-package:

(straight-use-package 'use-package)
(use-package verilog-ext)

Basic config

The most basic configuration just requires choosing which features you want to load, setup the minor-mode and add it as a hook for verilog-mode. By default all features are enabled:

;; Can also be set through `M-x RET customize-group RET verilog-ext':
;; Comment out/remove the ones you do not need
(setq verilog-ext-feature-list
      '(font-lock
        xref
        capf
        hierarchy
        eglot
        lsp
        lsp-bridge
        lspce
        flycheck
        beautify
        navigation
        template
        formatter
        compilation
        imenu
        which-func
        hideshow
        typedefs
        time-stamp
        block-end-comments
        ports))
(require 'verilog-ext)
(verilog-ext-mode-setup)
(add-hook 'verilog-mode-hook #'verilog-ext-mode)

If installed and loaded via use-package:

(use-package verilog-ext
  :hook ((verilog-mode . verilog-ext-mode))
  :init
  ;; Can also be set through `M-x RET customize-group RET verilog-ext':
  ;; Comment out/remove the ones you do not need
  (setq verilog-ext-feature-list
        '(font-lock
          xref
          capf
          hierarchy
          eglot
          lsp
          lsp-bridge
          lspce
          flycheck
          beautify
          navigation
          template
          formatter
          compilation
          imenu
          which-func
          hideshow
          typedefs
          time-stamp
          block-end-comments
          ports))
  :config
  (verilog-ext-mode-setup))

Keybindings

Enabling of verilog-ext-mode minor-mode creates the following keybindings:

• Features:

  • <kbd>C-c C-l</kbd> verilog-ext-formatter-run
  • <kbd>C-c <f5></kbd> verilog-ext-compile-project
  • <kbd>C-c C-p</kbd> verilog-ext-preprocess
  • <kbd>C-c C-f</kbd> verilog-ext-flycheck-mode
  • <kbd>C-c C-t</kbd> verilog-ext-hydra/body
  • <kbd>C-c C-v</kbd> verilog-ext-hierarchy-current-buffer
  • <kbd>C-<tab></kbd> verilog-ext-hs-toggle-hiding

• Code beautifying

  • <kbd>C-M-i</kbd> verilog-ext-beautify-block-at-point
  • <kbd>C-c C-b</kbd> verilog-ext-beautify-current-buffer

• Dwim navigation

  • <kbd>C-M-a</kbd> verilog-ext-nav-beg-of-defun-dwim
  • <kbd>C-M-e</kbd> verilog-ext-nav-end-of-defun-dwim
  • <kbd>C-M-d</kbd> verilog-ext-nav-down-dwim
  • <kbd>C-M-u</kbd> verilog-ext-nav-up-dwim
  • <kbd>C-M-p</kbd> verilog-ext-nav-prev-dwim
  • <kbd>C-M-n</kbd> verilog-ext-nav-next-dwim

• Module at point

  • <kbd>C-c M-.</kbd> verilog-ext-jump-to-module-at-point-def
  • <kbd>C-c M-?</kbd> verilog-ext-jump-to-module-at-point-ref

• Jump to parent module

  • <kbd>C-M-.</kbd> verilog-ext-jump-to-parent-module

• Port connections

  • <kbd>C-c C-c c</kbd> verilog-ext-ports-clean-blanks
  • <kbd>C-c C-c t</kbd> verilog-ext-ports-toggle-connect
  • <kbd>C-c C-c r</kbd> verilog-ext-ports-connect-recursively

• Syntax table override functions:

  • <kbd>TAB</kbd> verilog-ext-tab
  • <kbd>M-d</kbd> verilog-ext-kill-word
  • <kbd>M-f</kbd> verilog-ext-forward-word
  • <kbd>M-b</kbd> verilog-ext-backward-word
  • <kbd>C-<backspace></kbd> verilog-ext-backward-kill-word

Features

Tree-sitter

Some of the features that verilog-ext provides are based either on builtin verilog-mode Emacs lisp parsing or on tree-sitter verilog-ts-mode. These features are hierarchy extraction and project tags collection for completion and navigation of definitions and references.

Using tree-sitter as a backend is recommended as it is much faster, efficient and accurate than internal Emacs lisp parsing.

For information about installation of verilog-ts-mode check its repo.

Project management

The package provides the variable verilog-ext-project-alist to select which files belong to a specific project:

(setq verilog-ext-project-alist
      `(("ucontroller" ; Project name
         :root "/home/gonz/Repos/larumbe/ucontroller" ; supports remote dirs via Tramp
         :files ("src/my_block.sv"
                 "src/*.v") ; Multiple files can be specified through the glob pattern
         :dirs ("src/tb"
                "-r src/rtl" ; -r to add directories recursively
                "src/syn/*_block"
                "src/**/netlists") ; add all dirs that begin with "src" and end with "netlists"
         :ignore-dirs ("src/ignored_ip")
         :ignore-files ("src/some_ip/ignored_sim_netlist.v")
         :compile-cmd "make tb_top" ; command used to compile current project
         ;; `vhier' related properties
         :command-file "commands.f" ; vhier command file
         :lib-search-path nil)))    ; list of dirs to look for include directories or libraries

The different properties for each project entry determine which files will be used for some features of the package, such as completion, xref navigation, hierarchy extraction and compilation.

Syntax highlighting

For configuration information, see the wiki.

Find definitions and references

verilog-ext provides an xref backend to navigate definitions and references of current project.

For configuration information, see the wiki.

Auto-completion

Complete with tags from current project. Supports dot and scope completion for module signals, class attributes and methods.

For configuration information, see the wiki.

Hierarchy extraction

Hierarchy extraction of module at current buffer.

For configuration information, see the wiki.

Language Server Protocol

Auto-configure various SystemVerilog language servers for lsp-bridge, lsp-mode, eglot and lspce:

• hdl_checker
• svlangserver
• verible
• svls
• veridian

For configuration instructions, see the wiki

Linting

Support via flycheck for the following linters:

• Verilator
• Icarus Verilog
• Verible
• Slang
• Svlint
• Surelog
• Cadence HAL

For configuration and usage instructions, see the wiki

Beautify instances

Indent blocks and align parameters and ports of RTL instances.

Interactive functions:

• verilog-ext-beautify-block-at-point: <kbd>C-M-i</kbd>
• verilog-ext-beautify-current-buffer: <kbd>C-c C-b</kbd>

Batch-mode functions:

• verilog-ext-beautify-files
• verilog-ext-beautify-dir-files: uses tree-sitter if run with prefix arg <kbd>C-u</kbd>

Navigation

Features:

• Context aware dwim functions for RTL/Verification environments
• Navigate instances inside a module
• Jump to definition/references of module at point
• Jump to parent module

For detailed info see the wiki.

Templates

Select among snippets that cover most frequently used SystemVerilog constructs:

Insert instances in current module from file:

Create basic testbench environment from DUT file:

UVM Agent template:

Functions:

• verilog-ext-hydra/body: <kbd>C-c C-t</kbd>

Code formatter

Code-formatter setup via apheleia and verible-verilog-format.

See configuration in the wiki.

Compilation

Provides functions to perform compilations with syntax highlighting and jump to error, buffer preprocessing and makefile development:

• verilog-ext-compile-project: <kbd>C-c <f5></kbd>
• verilog-ext-preprocess: <kbd>C-c C-p</kbd>
• verilog-ext-compile-makefile

See configuration in the wiki.

Imenu

Support detection of instances and methods inside classes.

Instances:

Methods:

Find more information here.

Which-func

Enhanced which-func support: show current block/instance at point in the mode-line

Code folding

Code folding via hideshow: <kbd>C-<tab></kbd>

Typedefs

Add support for syntax-higlighting and alignment via verilog-pretty-declarations of user defined types and classes.

For configuration see wiki

Time-stamp

Automatic update of header timestamp after file saving.

• verilog-ext-time-stamp-mode

For configuration see wiki

Block-end comments

Auto convert block comments to names after file saving.

• verilog-ext-block-end-comments-to-names-mode

Port connections

Toggle connections of ports under instance at point

• verilog-ext-ports-toggle-connect: <kbd>C-c C-c t</kbd>
• verilog-ext-ports-connect-recursively: <kbd>C-c C-c r</kbd>
• verilog-ext-ports-clean-blanks: <kbd>C-c C-c c</kbd>

Misc

Wrapper functions to stop cursor at underscores without breaking indentation

• verilog-ext-forward-word: <kbd>M-f</kbd>
• verilog-ext-backward-word: <kbd>M-b</kbd>
• verilog-ext-kill-word: <kbd>M-d</kbd>
• verilog-ext-backward-kill-word: <kbd>C-<backspace></kbd> and <kbd>M-DEL</kbd>

Contributing

Contributions are welcome! Just stick to common Elisp conventions and run the ERT suite after testing your changes and before submitting a new PR.

For new functionality add new ERT tests if possible.

Consider sponsoring to help maintaining the project and for the development of new features. Thank you!

ERT Tests

Setup

To run the whole ERT test suite change directory to the verilog-ext root and make sure test-hdl Git submodule has been loaded:

git submodule update --init

Targets

Then run the default target:

$ make

To run a subset of tests (e.g. navigation):

$ make TESTS=navigation

To regenerate all the expected outputs for the tests:

$ make gen

To regenerate the expected outputs for a group of tests (e.g. navigation):

$ make gen TESTS=navigation

Other packages

• verilog-ts-mode: SystemVerilog Tree-sitter mode
• vhdl-ts-mode: VHDL Tree-sitter mode
• vhdl-ext: VHDL Extensions
• fpga: FPGA & ASIC Utilities for tools of major vendors and open source
• wavedrom-mode: edit and render WaveJSON files to create timing diagrams
• vunit-mode: Integration of VUnit workflow