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pcievhost

PCIe (1.0a to 2.0) Virtual host model for Verilog and SystemVerilog logic simulation environments.

The pcievhost model generates PCIe Physical, Data Link and Transaction Layer traffic for up to 16 lanes, controlled from a user C program, via a comprehensive API. It has configurable internal memory and configuration space models, and will auto-generate completions (configurably), with flow control, ACKs, and NAKS etc. The protocol itself is modelled in C and is integrated with a logic simulation using the VProc virtual processor. The diagram below shows the structure of the model which ultimately generates a stream of 8b10b encoded symbols, and processes the returned symbols.

pcievhost is bundled with verilog pcie link traffic display modules and an example test harness. The model has been tested with ModelSim/Questa, Vivado xsim and Verilator at the present time, though easily adpated for other simulators. The pcievhost model can also be configured to act as an endpoint via a parameter and with simple running user code—the model itself automatically generating responses to transactions. The diagram below shows the example test bench structure.

More information can be found in the documentation <code>doc/pcieVHost.pdf</code>