Awesome

ix_yukio

Yukio's interconnect

I'm a resident of the looking-glass world!! (Every figure in this page is mirrored by y-axis)

The modules are in src directory. There is a testbench for each module in testbench directory.

The unidirectional version is in unidir_src directory. Its README is also in that directory.

parameters

parameters from modules

• CLBIN ... number of input-bits to one CLB
• CLBOUT ... number of output-bits of one CLB
• CARRY ... number of carry-bits passed between CLBs
• WW ... unit word width
• MACDATAIN ... number of input-words to one MAC module (WW*MACDATAIN input bits)
• MACDATAOUT ... number of output-words of one MAC module
• MACCONTROLIN ... number of control-bits to one MAC module
• NCLBMAC ... number of CLB-rows per one MAC-row (MAC/CLB in terms of height)
• MEMDATAIN
• MEMDATAOUT
• MEMCONTROLIN
• NCLBMEM

parameters to top module

• N ... number of big-tiles vertically
• M ... number of big-tiles horizontally
• WS ... number of bits (tracks) in each single line
• WD ... number of bits in each double line. WD must be multiple of 2
• WG ... number of bits in each global line
• WN ... number of words in the line around MAC/MEM modules (WN * WW bits)
• CLBOS ... number of the switches to connect each output of CLB to the single line tracks
• CLBOD ... number of the switches to connect each output of CLB to the double line tracks
• CLBIOTYPE ... 0 -> anyside with MUX, 1 -> left to right or right to left with MUX, 2 -> divided (CLBIN and CLBOUT must be multiple of 4)
• CLBX ... a boolean value to toggle using direct connection between adjacent CLBs
• CARRYTYPE ... 0 -> anyside with MUX, 1 -> vertical two-way and horizontal one-way only at the top and bottom with MUX, 2 -> one-way meandering (top to bottom -> left to right -> bottom to top -> left to right -> ...)
• MCLB ... number of CLB-columns in a big-tileset. MCLB must be multiple of 2.
• NSB ... No horizontal line and SB when ROW%NSB != 0 (except near io block and MAC/MEM). CLBIOTYPE must not be 2 when NSB is not 1. This is for layered interconnect.
• NSBSB ... number of SBs connected to one DSB. NSBSB must be less than or equal to min(NCLBMAC, NCLBMEM).
• NMAC ... number of MAC modules in a big-tile
• NMEM ... number of MEM modules in a big-tile
• EXTIN ... number of external input-pins in each io block
• EXTOUT ... number of external output-pins in each io block
• EXTDATAIN ... number of external input-words in each data io block
• EXTDATAOUT ... number of external input-words in each data io block

I define a big-tile as a figure below. It has one column for MAC and MEM in the middle. There may be multiple MAC modules and MEM modules in one big-tile, then the MAC modules are placed upper than all of the MEM modules. On the edges of FPGA, there are io blocks, one for each SB on the edges, two for each SB at the corners. There are also data io blocks for DSBs.

fpga.v in fpgatop branch implements this, but it has problems and yet to be simulated. iverilog ran into internal errors (buffer overflaw) when I increased some parameters. verilator seems to have problems in 2D array. Anyway it might help you understand how these parameters should be treated.

modules

The signals starting with "c" represent configuration bits.

• transmission_gate.v

• transmission_gate_oneway.v

I use this cell when one of the data is not inout. This enables verilator to compile the modules. The cell design of this module would be the same as transmission_gate.v.

• switch_box_element_one.v

• switch_box_element_two.v

• disjoint_switch_box.v

• universal_switch_box.v

  • When W is even

  

  • When W is odd

  

• clb_switch_box.v

One universal switch box for single lines and the following circuit for double lines.

• vertical_disjoint_switch_box.v

This is used as a switch box where there is no horizontal line in layered interconnect.

• connection_block.v

The number of inputs of CLB is CLBIN, but only first CLBIN0(CLBIN1) bits are connected to the tracks. When CLBX, a boolean parameter, is 1, there are direct connections. The number of switches for each output is limited by a parameter, and the place of switches is shifted per output. The amount of the last shift is passed to the next connection block as a bias. Please notice the places of c31 and c32.

• data_connection_block.v

For data input/output for MAC/MEM.

• control_connection_block.v

For control (address) input for MAC/MEM.

• io_block.v

• data_io_block.v

• switch_box_connector.v

Just connecting wires under modulus. Short circuit should not happen because the other end of wire can be 1'bz in switch boxes.