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uxn-fpga

Very early work in progress implementation of Varvara / UXN by hundredrabbits in FPGA using PipelineC. Intended for importing into the openfpga-varvara core for Analogue Pocket.

Change test ROM (for GHDL simulation):

Currently several ROMs are available as C arrays within .h files in the roms/ directory:

To use a different ROM for GHDL simulation, just change the import statement in uxn.c to import the correct ROM, and set DEBUG = 1 in uxn_constants.h.

build into VHDL files (for later importing into openfpga-uxn project for Analogue Pocket):

pipelinec uxn.c

build for GHDL simulation (requires additional plugins)

pipelinec uxn.c --sim --comb --ghdl

run GHDL simulation:

ghdl -i --std=08 --work=work [sequence of vhd files appended by top_test.vhd]
ghdl -m --std=08 --work=work top_test
ghdl -r --std=08 --work=work top_test --ieee-asserts=disable --stop-time=1ms