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litexOnColorlightLab004

Demonstration on using a Soft Core (VexRiscv) built with LiTex in a Colorlight 5A-75B or Colorlight I5 (ECP5). This demo is based on lab004 of fpga_101 repository.

Colorlight 5A-75B

UART use (arbitrary) J1 pins 1 & 2

namePinnote
clk25P625MHz clock
cpu_resetP11button J28
user_ledP11button J28
Uart TXF3J1.1
Uart RXF1J1.2

Colorlight I5

UART is directly available through CMSIS-DAP ACM interface

namePinnote
clk25P325MHz clock
cpu_reset_nK18button J28
user_ledU16button J28
Uart TXJ17CMSIS-DAP
Uart RXH18CMSIS-DAP

Prerequisite

software

hardware (Colorlight 5A-75B only)

JX direct connection

U28 without buffer and with direct connection between input and output.

Build

gateware

Just:

./base.py --version 5A-75B --build

or

./base.py --version i5 --build

firmware

cd firmware && make [VERSION=5a_75b]

where VERSION may be 5a_75b or i5

see lab004 for more details.

load bitstream

./base.py --version 5A-75B --load [--cable yourCable] # change 5A-75B by I5

where yourCable depends on your JTAG probe. If --cable is not provided openFPGALoader will uses ft2232 generic interface. Not required for I5.

load firmware

litex_term /dev/ttyYYYX --kernel firmware/firmware.bin

where ttyYYYX is your USB <-> UART converter device (usually ttyUSB0 (5A-75B) or ttyACM0 (I5)).

boot

serialboot

test

To start the blink led use command

led