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Exemplary NEORV32 Setups and Projects

Community Projects (hardware / software)
Setups using Commercial Toolchains (FPGA setups)
Setups using Open-Source Toolchains (FPGA setups)
Adding Your Project or Setup
Setup-Specific NEORV32 Software Framework Modifications

This repository provides community projects as well as exemplary setups for different FPGAs, platforms, boards and toolchains for the NEORV32 RISC-V Processor. Project maintainers may make pull requests against this repository to add or link their setups and projects.

[!TIP] Ready-to-use bitstreams for the provided open source toolchain-based setups are available via the assets of theImplementation Workflow.

Community Projects

This list shows projects that focus on custom hard- or software modifications, specific applications, etc.

Link	Description	Author(s)
:earth_africa: github.com/motius	tutorial: custom CRC32 processor module for the nexys-a7 boards	motius (ikstvn, turbinenreiter)
:earth_africa: neorv32-examples	NEORV32 setups/projects for different Intel/Terasic boards	emb4fun
:earth_africa: neorv32-xmodem-bootloader	A XModem Bootloader for the DE0-Nano board	emb4fun
:earth_africa: neorv32-xip-bootloader	A XIP (eXecute In Place) Bootloader for the NEORV32	betocool-prog

Setups using Commercial Toolchains

The setups using commercial toolchains provide pre-configured project files that can be opened with the according FPGA tools.

Setup	Toolchain	Board	FPGA	Author(s)
:file_folder: `de0-nano-test-setup`	Intel Quartus Prime	Terasic DE0-Nano	Intel Cyclone IV `EP4CE22F17C6N`	stnolting
:file_folder: `de0-nano-test-setup-qsys`	Intel Quartus Prime	Terasic DE0-Nano	Intel Cyclone IV `EP4CE22F17C6N`	torerams
:file_folder: `de0-nano-test-setup-avalonmm`	Intel Quartus Prime	Terasic DE0-Nano	Intel Cyclone IV `EP4CE22F17C6N`	torerams
:file_folder: `terasic-cyclone-V-gx-starter-kit-test-setup`	Intel Quartus Prime	Terasic Cyclone-V GX Starter Kit	Intel Cyclone V `5CGXFC5C6F27C7N`	zs6mue
:file_folder: `UPduino_v3`	Lattice Radiant	tinyVision.ai Inc. UPduino `v3.0`	Lattice iCE40 UltraPlus `iCE40UP5K-SG48I`	stnolting
:file_folder: `iCEBreaker`	Lattice Radiant	iCEBreaker @ GitHub	Lattice iCE40 UltraPlus `iCE40UP5K-SG48I`	stnolting
:file_folder: `arty-a7-35-test-setup`	Xilinx Vivado	Digilent Arty A7-35	Xilinx Artix-7 `XC7A35TICSG324-1L`	stnolting
:file_folder: `nexys-a7-test-setup`	Xilinx Vivado	Digilent Nexys A7	Xilinx Artix-7 `XC7A50TCSG324-1`	AWenzel83
:file_folder: `nexys-a7-test-setup`	Xilinx Vivado	Digilent Nexys 4 DDR	Xilinx Artix-7 `XC7A100TCSG324-1`	AWenzel83
:file_folder: `on-chip-debugger-intel`	Intel Quartus Prime	Gecko4Education	Intel Cyclone IV E `EP4CE15F23C8`	NikLeberg
:file_folder: `tang-nano-9k`	Gowin EDA	Sipeed Tang Nano 9K	Gowin LittleBee GW1NR-9 `GW1NR-LV9QN88PC6/I5`	IvanVeloz

Setups using Open-Source Toolchains

Most OSS setups using open-source toolchains are located in the osflow folder. See the README there for more information how to run a specific setup and how to add new targets.

Setup	Toolchain	Board	FPGA	Author(s)
:file_folder: `UPDuino-v3.0`	GHDL, Yosys, nextPNR	UPduino v3.0	Lattice iCE40 UltraPlus `iCE40UP5K-SG48I`	tmeissner
:file_folder: `FOMU`	GHDL, Yosys, nextPNR	FOMU	Lattice iCE40 UltraPlus `iCE40UP5K-SG48I`	umarcor
:file_folder: `iCESugar`	GHDL, Yosys, nextPNR	iCESugar	Lattice iCE40 UltraPlus `iCE40UP5K-SG48I`	umarcor
:file_folder: `AlhambraII`	GHDL, Yosys, nextPNR	AlhambraII	Lattice iCE40HX4K	zipotron
:file_folder: `Orange Crab`	GHDL, Yosys, nextPNR	Orange Crab	Lattice ECP5-25F	umarcor, jeremyherbert
:file_folder: `ULX3S`	GHDL, Yosys, nextPNR	ULX3S	Lattice ECP5 `LFE5U-85F-6BG381C`	zipotron
:file_folder: `GateMateA1-EVB`	GHDL, Yosys, CC P_R	GateMateA1-EVB(-2M)	Cologne Chip GateMate `CCGM1A1`	stnolting
:file_folder: ChipWhisperer `iCE40CW312`	GHDL, Yosys, nextPNR	CW312T_ICE40UP	Lattice iCE40 UltraPlus `iCE40UP5K-UWG30`	colinoflynn
:earth_africa: `ULX3S-SDRAM`	GHDL, Yosys, nextPNR	ULX3S	Lattice ECP5 `LFE5U-85F-6BG381C`	zipotron

Adding Your Project or Setup

Please respect the following guidelines if you'd like to add or link your setup/project to the list:

check out the project's code of conduct
for FPGA- / board- / toolchain-specific setups:
- a "setup" is a wrapped (and maybe script-aided) implementation of the NEORV32 processor for a certain FPGA/board/toolchain
- add a link if the board you are using provides online documentation or can be purchased somewhere
- use the :file_folder: emoji (:file_folder:) if the setup is located in this repository; use the :earth_africa: emoji (:earth_africa:) if it is a link to your local project
- please add a README.md file to give some brief information about the setup and a .gitignore file to keep things clean
- for local setups you can add your setup to the implementation GitHub actions workflow to automatically generate up-to-date bitstreams for your setup
for projects:
- provide a link to your project (use the :earth_africa: (:earth_africa:) emoji)
- provide a short description
- further information should be provided by a project-local README

Setup-Specific NEORV32 Software Framework Modifications

In order to use the features provided by the setups, minor optional changes can be made to the default NEORV32 setup.

To change the default data memory size take a look at the User Guide section General Software Framework Setup
To modify the SPI flash base address for storing/booting software application see User Guide section Customizing the Internal Bootloader