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RISC-V Debug task group

The RISC-V Debug Task Group was established to propose specifications for debug on RISC-V implementations. The scope of the group includes run-control and trace debug, but the current focus is to agree upon a standard for run-control debug.

The group is currently chaired by Megan Wachs (SiFive Inc).

As of the 22nd March 2017, future notes, slides, and discussions will be moved to the RISC-V members workspace.

Run-control debug

Run-control debug allows you to halt, step, resume, to set breakpoints, and to access GPRs+CSRs+memory. There have been two main proposals for run-control, and much of the group's time has been spent understanding the differences and trade-offs between these two approaches, with the goal of producing a single unified specification.

Working draft

The debug specification is developed in the riscv-debug-spec Github repository. PDF versions are periodically generated and published here.

Meetings

In addition to discussions on the mailing list, the group has held a series of meetings. As of the 22nd March 2017, future notes, slides, and discussions will be moved to the RISC-V members workspace.

Previous

Historical specification development

Previously, the task group went through detailed discussion on a number of different approaches. The key documents produced in that process are linked below.