Awesome

Analog-Design-of-1.9-GHz-PLL-system

This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.

[1] PLL System Design

• PLL block diagram: <br/> <br/> <br/>
• Typical CP PLL system: <br/> <br/> <br/>
• System Parameters: <br/> <br/> <br/>
• System Stability: <br/> <br/> <br/> <br/> <br/>
• Open-Loop & Closed-Loop Parameters: <br/> <br/> <br/>
• VerilogA System Simulation: <br/><br/> <br/> <br/> <br/> <br/>

[2] PLL Circuit Design

A) PFD:

B) Charge Pump:

<br/> <br/>

C) Loop Filter:

<br/>

D) VCO:

1- LC VCO:

Refer to: https://github.com/muhammadaldacher/RF-design-of-1.9-GHz-Rx-frontend/tree/master/%5B2%5D%20VCO%20design <br/> <br/> <br/>

2- Current-Starved Ring VCO:

Refer to: https://drive.google.com/drive/folders/1fyUhUR0x1b1HQYjlndnEte-GhuKZ9sJ6 <br/> <br/> <br/>

E) Divider:

<br/>

1- TSPC Flipflop: (for high-speed-input stages)

<br/>

2- CMOS Flipflop: (for lower-speed-input stages)

<br/><br/>

=> System Simulations:

• Testbench: <br/> <br/><br/> 1- With LC VCO:<br/><br/> <br/> <br/><br/> 2- With Ring VCO:<br/><br/> <br/> <br/><br/>
• Comparison: <br/> <br/>
• Corner Simulations (using LC VCO): <br/> <br/><br/><br/>

References:

-> VerilogA References:<br/> https://github.com/muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system/tree/master/%5B1%5D%20PLL%20System%20Level%20(VerilogAMS%20-%20Matlab)/VerilogA%20References%20(for%20PLLs) <br/> -> PLL Design References: <br/> https://github.com/muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system/tree/master/%5B2%5D%20PLL%20Circuit%20Design/References <br/> My project on google drive:<br/> https://drive.google.com/drive/folders/1TUYCLbdZC5S4dQVAxZmoUjMQPiLFntPe <br/> EE230 Lecture Notes:<br/> https://drive.google.com/open?id=1WcP2svOrAle0cEzlL1oexYeuDEQjH5j9 <br/> SGFET Nanowire PLL design:<br/> https://drive.google.com/open?id=11aUuht1qpGR8_nj85TnPhnZkIp3dgVg7 <br/><br/> [Thesis] "DESIGN OF A PHASE LOCKED LOOP BASED CLOCKING CIRCUIT FOR HIGH SPEED SERIAL LINK APPLICATIONS" by RISHI RATAN: <br/> https://www.ideals.illinois.edu/items/49560 <br/>