Awesome

The EPFL Combinational Benchmark Suite

The EPFL Combinational Benchmark Suite was introduced in 2015 with the aim of defining a new comparative standard for the logic optimization and synthesis community. It originally consisted of 23 combinational circuits designed to challenge modern logic optimization tools. The benchmark suite is divided into arithmetic, random/control and MtM circuits, and each circuit is distributed in Verilog, VHDL, BLIF and AIGER formats.

Arithmetic Benchmarks
The EPFL benchmark suite has 10 arithmetic benchmarks. They are obtained by an automated mapping of arithmetic computational algorithms into basic logic gates. Examples are square-root, divisor, multipliers, adder, etc; they come in different bit-widths to provide diversity in the implementation complexity. The initial implementations are intendedly sub-optimal to test the ability of optimization tools. LUT-6 mapping experiments for the arithmetic EPFL combinational benchmarks are listed in the following Table. They are performed using ABC academic tool, with the mapping command if -K 6.

Random/Control Benchmarks
The EPFL benchmark suite has 10 random/control benchmarks. They include various types of controllers, arbiters, routers, converters, decoders, voters and random functions, mapped into simple gates from their behavioral descriptions. Also here, the initial implementations are intendedly unoptimized. LUT-6 mapping experiments for the random/control EPFL combinational benchmarks are listed in the following Table. They are performed using ABC academic tool, with the mapping command if -K 6.

More than ten Miliong gates (MtM) Benchmarks
The EPFL benchmark suite has 3 MtM benchmarks. These benchmarks are designed to challenge the size capacity of modern optimization tools; they are extracted from a set of random Boolean functions, generated with a custom computer program, using as selection metric the implementation complexity. LUT-6 mapping experiments for the MtM EPFL combinational benchmarks are listed in the following Table. They are performed using ABC academic tool, with the mapping command if -K 6.

The MtM benchmarks can be downloaded at https://zenodo.org/record/2572934#.XGxRiS3MzuM

Best LUT-6 implementation

We keep track of the best optimization results, mapped into LUT-6, for size and depth metrics.

Submit your best LUT-6 implementation!

We encourage researchers to submit their best LUT-6 implementations in BLIF format for one or more of the benchmarks:

• at benchmarks@groupes.epfl.ch (in case the files exceed 3 MB please provide a download link in the email)
• or with a pull request to this repository.

Also the methodology used to optimize/map the circuits needs to be specified. We will run combinational equivalence checking and verify the claimed improvements over the current best implementation. If passing all tests, we will publish online the circuit together with the author’s name and affiliation as symbolic recognition.

The results presented above are NOT the best results, but they are the ORIGINAL benchmarks. All best known results can be found at the tags on this repository.

Submission deadline 2025

The latest best results for the 2024 competition have been published. Results for the 2025 competition will be collected a few weeks before IWLS 2025, with more details to be announced later.

References

The EPFL combinational benchmarks are explained in the paper The EPFL Combinational Benchmark Suite, presented at the International Workshop on Logic Synthesis 2015

Other benchmark sets

Multi-output PLA benchmarks are a set of 9 multiple-output PLA tables taken from an instruction decoder. These PLA files were used in the paper B. Schmitt, A. Mishchenko, V. Kravets, R. Brayton, and A. Reis, "Fast-extract with cube hashing", Proc. ASP-DAC'17 and can be downloaded at https://people.eecs.berkeley.edu/~alanmi/benchmarks/table_ex/