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neon2rvv
A C/C++ header file that converts Arm/Aarch64 NEON intrinsics to RISC-V Vector (RVV) Extension.
Introduction
neon2rvv is a translator of Arm/Aarch64 NEON intrinsics to RISC-V Vector (RVV) Extension, shortening the time needed to get an RISCV working program that then can be used to extract profiles and to identify hot paths in the code. The header file neon2rvv.h contains several of the functions provided by NEON intrinsic header, <arm_neon.h>, only implemented with RISCV-based counterparts to produce the exact semantics of the intrinsics.
Usage
-
Put the file
neon2rvv.hin to your source code directory. -
Replace the header file
arm_neon.hwithneon2rvv.h.#include "neon2rvv.h" -
Explicitly specify platform-specific options to gcc/clang compilers
-march=rv64gcv_zba
Targets and Limitations
The preliminary stage development goal of neon2rvv is targeting RV64 architecture with 128 bits vector register size (vlen == 128), which means the implementation is compiled with -march=rv64gcv_zba flag.
We are using RISC-V GNU Compiler Toolchain for development.
Development
Run Tests
neon2rvv provides a unified interface for developing test cases. These test cases are located in tests directory, and the input data is specified at runtime. Use the following commands to perform test cases:
You can run the tests under the architecture of your current machine. This can help you verify the implementation of tests case if you run the tests on ARM machines. Now the tests support Aarch64 only.
$ make test
You can specify GNU toolchain for cross compilation as well. For simulator, RISC-V ISA Simulator, Spike is used in default.
$ make CROSS_COMPILE=riscv64-unknown-elf- check # rv64
For developers who wants to run the cross-compiled tests with qemu-riscv64, you can specify QEMU with following command.
$ make CROSS_COMPILE=riscv64-unknown-elf- SIMULATOR_TYPE=qemu test
Official Documents
- riscv-v-spec
- rvv-intrinsic-doc
- riscv-c-api
- NEON Intrinsics
- Coding for Neon: