Awesome

Verik Examples

Examples for Verik. Refer to template for a template project. Compiling the examples requires a local build of the Verik toolchain.

riscv

RISC-V core adapted from the PicoRV32 project. PicoRV32 is a CPU core that implements the RV32IMC instruction set. It is configurable with an optional interrupt controller, single or two-cycle ALU, and single or dual-port register file. Tags: #Modules #Parameterization #Assertions

fpga

Examples that are meant to be run on the Nexys 4, a development board with an Artix-7 FPGA. These examples are synthesized with Xilinx Vivado and may integrate Vivado IP.

01-sevenseg

Simple seven-segment display driver with test bench. Tags: #FPGA #Modules

02-camera

Write data from a camera into block memory and read from the memory to drive a VGA display. Tags: #FPGA #Modules

03-fft

Read audio input from an ADC, perform an FFT, and plot the magnitudes on a VGA display. Tags: #FPGA #Modules

uvmprimer

Examples adapted from The UVM Primer that demonstrate OOP testbench functionality. These examples import from the UVM and closely follow the original SystemVerilog coding conventions rather than the coding conventions of idiomatic Verik. Warnings from code style violations are suppressed with @file:Suppress annotations at the top of the source files. To compile these examples define the environment variable UVM_HOME and point it to uvm/distrib.

01-conventional-test

Conventional testbench for an ALU. Tags: #Modules #Coverage

02-interfaces

Interfaces and bus functional models for an ALU. Tags: #Modules #ModuleInterfaces #Coverage

03-classes

Classes and inheritance for a rectangle class. Tags: #Classes

04-polymorphism

Polymorphic types for an animal class. Tags: #Classes

05-static-methods

Static methods with objects. Tags: #Classes

06-type-parameters

Type parameterized classes. Tags: #Classes #Parameterization

07-factory-pattern

Factory pattern for object instantiation. Tags: #Classes #Parameterization

08-oop-test

Basic OOP testbench for an ALU. Tags: #Modules #ModuleInterfaces #Classes #Coverage

09-uvm-test

Basic UVM testbench for an ALU. Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage

10-uvm-components

UVM testbench for an ALU with UVM components. Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage

11-uvm-environments

UVM testbench for an ALU with UVM environments. Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage

12-analysis-ports

Dice roller example with UVM analysis ports. Tags: #Importer #UVM #Coverage #Randomization

13-analysis-ports-test

UVM testbench for an ALU with UVM analysis ports. Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage

14-communication

Interthread communication with UVM put and get ports. Tags: #Importer #UVM

15-communication-test

UVM testbench for an ALU with UVM put and get ports. Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage

16-uvm-reporting

UVM testbench for an ALU with UVM reporting macros. Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage

17-deep-operations

Deep operations for copying and converting objects to strings. Tags: #Classes

18-uvm-transactions

UVM testbench for an ALU with UVM transactions. Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage #Randomization

19-uvm-agents

UVM testbench for an ALU with UVM agents. Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage #Randomization

20-uvm-sequences

UVM testbench for an ALU with UVM sequences. Tags: #Importer #Modules #ModuleInterfaces #UVM #Coverage #Randomization

vkprimer

Examples from uvmprimer rewritten to follow the coding conventions of idiomatic Verik. These examples do not import from the UVM and implement the equivalent functionality directly in Verik.

01-conventional-test

Conventional testbench for an ALU. Tags: #Modules #Coverage

02-interfaces

Interfaces and bus functional models for an ALU. Tags: #Modules #ModuleInterfaces #Coverage

03-classes

Classes and inheritance for a rectangle class. Tags: #Classes

04-polymorphism

Polymorphic types for an animal class. Tags: #Classes

05-static-methods

Static methods with objects. Tags: #Classes

06-type-parameters

Type parameterized classes. Tags: #Classes #Parameterization

07-factory-pattern

Factory pattern for object instantiation. Tags: #Classes #Parameterization

08-oop-test

Basic OOP testbench for an ALU. Tags: #Modules #ModuleInterfaces #Classes #Coverage

17-deep-operations

Deep operations for copying and converting objects to strings. Tags: #Classes

svverif

Examples adapted from SystemVerilog for Verification that demonstrate more verification features. These examples follow the coding conventions of idiomatic Verik.

01-arbiter

Arbiter testbench with a module interface that demonstrates module ports and clocking blocks. Tags: #Modules #ModuleInterfaces

02-unique-array

Generate an random array with unique elements. Tags: #Classes #Randomization

03-atm-switch

ATM switch with test bench. The number of RX and TX streams is parameterized. Tags: #Modules #ModuleInterfaces #Classes #Parameterization #Randomization

04-utopia-atm-switch

UTOPIA bus ATM switch with testbench. This example is currently work in progress. Tags: #Modules #ModuleInterfaces #Classes #Parameterization #Coverage #Randomization

misc

Miscellaneous examples that demonstrate various aspects of the language.

01-count

Simple counter module. Tags: #Module

02-adder

Simple parameterized ripple-carry adder module. Tags: #Module #Parameterization

03-multiplier

Simple combinational and sequential multipliers. Tags: #Module

04-comb

Various combinational logic expressed with simple logic gates. Tags: #Module

05-alu

Simple RV32I ALU with tests. Tags: #Module

06-cache

Direct mapped write-back cache. Tags: #Module #ModuleInterface