Awesome
Logic Simulator
** Deprecated: see Logic 2 **
An IDE for experimentation with Francis Stokes (Low Level Javascript) Digital Circuit Simulator
Installation
npm install
quasar dev
Features
- Micro-subset verilog-like DSL for coding the array of logic gates (Parsed using Arcsecond.js of course!)
- CodeMirror-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
- Visualisation of the generated gate array by hierachical table or a (experimental toy really) dagre graph
- Testbench simulation with graphical trace output
- Coming soon: d3-hwschematic view with simulation state animation
DSL
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Modules define a group of gates (eg a logic chip) and the inputs and outputs (eg the pins) between modules
module MyModule(input A, input B, output Q) // gate, wire and instance statements here endmodule
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Gates define a basic logic function, a unique identifier for this gate, and the inputs to the gate
wire myAndGate; and(myAndGate, A, B); // equivalent to myAndGate = A & B
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Instances of gates define a namespaced copy of a module and the connections between the parent module and the instance module
MyModule m1(.A(parentVar1), .B(parentVar2), .Q(parentVar3))
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All programs must have a "main" module which is automatically instanced and serves as the entry point.
a) The main module automatically includes a "clock" input.
b) The inputs to the main module will be external "control" gates eg buttons/sensors
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The main module should include a testbench section to define the value of the control gates at different time points
test begin #00 {a=0, b=0}; #05 {a=0, b=1}; #10 {a=1, b=0}; #15 {a=1, b=1}; end
TODO
- More sample code circuits
One hot encoder2 to 1 multiplexer2_17 segment encoder1 bit adderD flip-flop- 4 bit ripple adder
- 4 to 1 multiplexer with bit vector select line
- Ripple counter
- Shift register
- FSMs
Support bitwise statements to generate the logic gateseg Q = (A & B) | ~C- Reuse intermediary gates
- Support bit vector type
Improve traces with time slider to animate stateImprove schematic with time slider to animate state- Experiment with better schematic graph layouts, custom combo
- More linting
Code hints (Ctrl-Space),snippets (Ctrl-Shift-Space),comment hotkey,- Future? a) Truth tables to generate optimised logic gates