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Vector Technology as Implemented for Use with a RISC and SIMD Technology Signal Processor

A vector processor uses long registers addressable by segment-precision, where each segment is n bits wide. The power of a vector processor is that many complex matrix operations, whose algorithms take many scalar CPU instructions and clock cycles to emulate on a regular, personal computer processor, can often times formulate and transfer the correct result in less than a single clock cycle. The impossibility to replicate this precise behavior has paved the way for vendor businesses to protect their systems against hardware emulation since the introduction of display devices rendering three-dimensional graphics. The Nintendo 64 was the first video game system to employ this convenience to their advantage.

Project Reality's Signal Processor

In the engineering make-up of the Nintendo 64 (original codename: Project Reality) is a modified MIPS family revision 4000 co-processor called the "Reality Coprocessor" (RCP). More importantly, the signal processor in this component is responsible for all vector memory operations and transactions, which are almost all impossible to emulate with full accuracy on a scalar, personal computer processor. The vector technology implemented into this design is that accepted from Silicon Graphics, Inc.

RSP Vector Operation Matrices

Here, the entire MIPS R4000 instruction set was modified for very fast, exception-free processing flow, and operation definitions for each instruction do not fall within the scope of this section. Presented instead are layouts of the new instructions added to the scalar unit (those under LWC2 and SWC2, even though they do interface with the vector unit) and the vector unit (essentially, any instruction under COP2 whose mnemonic starts with a 'V'). Information of how pre-existing MIPS R4000 instructions were modified or which ones were removed is the adventure of the MIPS programmer to research.

C2 vd, vs, vt[element] /* exceptions: scalar divide reads */

COP2elementvs1vs2vtfunc
0100101eeeetttttsssssddddd??????

The major types of VU computational instructions are multiply, add, select, logical, and divide.

Multiply instructions are the most frequent and classifiable as follows:

op-codeType
00axxxmultiply
01xxxxadd
100xxxselect
101xxxlogical
110xxxdivide

RSP Vector Load Transfers

The VR-DMEM transaction instruction cycles are still processed by the scalar unit, not the vector unit. In the modern implementations accepted by most vector unit communications systems today, the transfer instructions are classifiable under five groups:

  1. BV, SV, LV, DV
  2. PV, UV, XV, ZV
  3. HV, FV, AV
  4. QV, RV
  5. TV, WV

Not all of those instructions were implemented as of the time of the Nintendo 64's RCP, however. Additionally, their ordering in the opcode matrix was a little skewed to what is seen below. At this time, it is better to use only three categories of instructions:

LWC2 vt[element], offset(base)

LWC2basevtrdelementoffset
110010sssssttttt?????eeeeXxxxxxx

SWC2 vt[element], offset(base)

SWC2basevtrdelementoffset
111010sssssttttt?????eeeeXxxxxxx

If, by any chance, the opcode specifier is greater than 17 [oct], it was probably meant to execute the extended counterparts to the above loads and stores, which were questionably obsolete and remain reserved.

Informational References for Vector Processor Architecture

Instruction Methods for Performing Data Formatting While Moving Data Between Memory and a Vector Register File United States patent no. 5,812,147 Timothy J. Van Hook Silicon Graphics, Inc.

Method and System for Efficient Matrix Multiplication in a SIMD Processor Architecture United States patent no. 7,873,812 Tibet Mimar

Efficient Handling of Vector High-Level Language Constructs in a SIMD Processor United States patent no. 7,793,084 Tibet Mimar

Flexible Vector Modes of Operation for SIMD Processor patent pending? Tibet Mimar

Programming a Vector Processor and Parallel Programming of an Asymmetric Dual Multiprocessor Comprised of a Vector Processor and a RISC Processor United States patent no. 6,016,395 Moataz Ali Mohamed Samsung Electronics Co., Ltd.

Execution Unit for Processing a Data Stream Independently and in Parallel United States patent no. 6,401,194 Le Trong Nguyen Samsung Electronics Co., Ltd.