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Description

The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX. The core was modeled and tested based on the Bochs software x86 implementation. Together with the 486 core, the ao486 project also contains a SoC capable of booting the Linux kernel version 3.13 and Microsoft Windows 95.

Current status

Features

The ao486 processor model has the following features:

The ao486 SoC consists of the following components:

All components are modeled as Altera Qsys components. Altera Qsys connects all parts together, and supplies the SDRAM controller.

The ao486 project is currently only running on the Terasic DE2-115 board.

Resource usage

The project is synthesised for the Altera Cyclone IV E EP4CE115F29C7 device. Resource utilization is as follows:

UnitLogic cellsM9K memory blocks
ao486 processor3651747
floppy15142
hdd207117
nios210563
onchip for nios2032
pc_dma8480
pic3880
pit6670
ps27422
rtc7831
sound3713129
vga2534260

The fitter raport after compiling all components of the ao486 project is as follows:

Fitter Status : Successful - Sun Mar 30 21:00:13 2014
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : soc
Top-level Entity Name : soc
Family : Cyclone IV E
Device : EP4CE115F29C7
Timing Models : Final
Total logic elements : 91,256 / 114,480 ( 80 % )
    Total combinational functions : 86,811 / 114,480 ( 76 % )
    Dedicated logic registers : 26,746 / 114,480 ( 23 % )
Total registers : 26865
Total pins : 108 / 529 ( 20 % )
Total virtual pins : 0
Total memory bits : 2,993,408 / 3,981,312 ( 75 % )
Embedded Multiplier 9-bit elements : 44 / 532 ( 8 % )
Total PLLs : 1 / 4 ( 25 % )

The maximum frequency is 39 MHz. The project uses a 30 MHz clock.

CPU benchmarks

The package DosTests.zip from http://www.roylongbottom.org.uk/dhrystone%20results.htm was used to benchmark the ao486.

TestResult
Dhryston 1 Benchmark Non-Optimised1.00 VAX MIPS
Dhryston 1 Benchmark Optimised4.58 VAX MIPS
Dhryston 2 Benchmark Non-Optimised1.01 VAX MIPS
Dhryston 2 Benchmark Optimised3.84 VAX MIPS

Running software

The ao486 successfuly runs the following software:

BIOS

The ao486 project uses the BIOS from the Bochs project (http://bochs.sourceforge.net, version 2.6.2). Some minor changes were required to support the hard drive.

The VGA BIOS is from the VGABIOS project (http://www.nongnu.org/vgabios, version 0.7a). No changes were required. The VGA model does not have VBE extensions, so the extensions were disabled.

NIOS2 controller

The ao486 SoC uses a Altera NIOS2 processor for managing all components and displaying the contents of the On Screen Display.

The OSD allows the user to insert and remove floppy disks.

License

All files in the following directories:

are licensed under the BSD license:

All files in the following directories:

are taken from the Bochs Project and are licensed under the LGPL license.

The binary file sd/fd_1_44m/fdboot.img is taken from the FreeDOS project.

The binary file sd/bios/bochs_legacy is a compiled BIOS from the Bochs project.

The binary file sd/vgabios/vgabios-lgpl is a compiled VGA BIOS from the vgabios project.

Compiling

To compile the SoC, which contains the NIOS II microcontroller, Altera Quartus II software is required. The Verilog components of the SoC, in particular the ao486 processor, should be possible to compile in any Verilog compiler. Currently synthesis project files are prepared only for Altera Quartus II.

NOTE: In the current version some synthesis project files -- especially the paths in those files, could be broken.

ao486 processor

To compile the ao486 processor load the project file from syn/components/ao486/ao486.qpf.

SoC

To compile the ao486 SoC load the project file from syn/soc/soc.qpf.

Before compiling in Altera Quartus II, the Qsys system must be generated.

BIOS

To compile the BIOS do the following:

VGABIOS

To compile the VGABIOS do the following:

Running the SoC on Terasic DE2-115