Awesome

Awesome VHDL

A curated list of awesome VHDL IP cores, frameworks, libraries, software and related resources.

Table of content:

• Libraries
  • IP Core Libraries
  • IP Core Collections
• IP Cores
• Frameworks
  • Verification Frameworks
• Verification Models
  • Memory Models
  • Interface Models
• Tools
  • Grammars
  • Parsers
  • Simulators
  • Package Managers
• Services
  • Code Quality
  • Continuous Integration
  • Continuous Documentation
• Resources
  • Books
  • Podcasts
  • Twitter
  • Websites
  • Weekly
• Other Awesome Lists
• Contributing

Libraries

IP Core Libraries

Libraries containing multiple IP cores.

• The PoC-Library - A library of free, open-source and platform independent IP cores.

IP Core Collections

Collections containing multiple IP cores.

IP Cores

Single IP cores.

Frameworks

Verification Frameworks

Frameworks for Verification.

• Open Source VHDL Verification Methodology (OSVVM)
• Universal VHDL Verification Methodology (UVVM)

Verification Models

Single verification models.

Memory Models

Verification Model for Memories

Interface Models

Verification Model for Interfaces.

Tools

Grammars

Parsers

Simulators

• GHDL - A free and open source VHDL simulator supporting VHDL-87/93/2002/2008.

Package Managers

Services

Code Quality

Continuous Integration

Continuous Documentation

Resources

Books

Twitter

Websites

Weekly

Other Awesome Lists

List of lists.

• awesome
• awesome-hdl

Contributing

Your contributions are always welcome! Please take a look at the contribution guidelines first.

I will keep some pull requests open if I'm not sure whether those libraries are awesome, you could vote for them by adding :+1: to them. Pull requests will be merged when their votes reach 10.

License

Creative Commons - CC0 1.0 Universal (CC0 1.0)

If you have any question about this opinionated list, do not hesitate to contact me @PaebbelsLemmi on Twitter or open an issue on GitHub.