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Lake: An Agile Framework for Designing and Automatically Configuring Physical Unified Buffers

Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros. Lake also comprises a library of generalized hardware modules aimed at memory controller designs.

Install

git clone github.com/StanfordAHA/lake

cd lake && pip install -e .

Run a test

To run a test, you can simply generate the verilog and push through your favorite verilog simulator. Alternatively, Lake uses the pytest framework for unit tests of constituent modules. These tests leverage fault and verilator for open source simulation. Tests should run and pass on Linux and MacOS.

Documentation

Check out the wiki of this github repo.