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MatchLib is a SystemC/C++ library of commonly-used hardware functions and components that can be synthesized by most commercially-available HLS tools into RTL.

Doxygen-generated documentation can be found here.

MatchLib is based on the Connections latency-insensitive channel implementation. Connections is included with the Catapult HLS tool and is available open-source on HLSLibs. Additional documentation on the Connections latency-insensitive channel implementation can be found in the Connections Guide.

Getting Started

Tool versions

MatchLib is regressed against the following tool/dependency versions:

Environment requirements

Makefiles assume the appropriate definition of the following environment variables:

In addition, the boost and systemc library locations are expected to be in LD_LIBRARY_PATH.

Build and run

C++ compile and simulate

cd cmod/<module>
make
make run

C++ compile and simulate all

cd cmod
make -f regress_Makefile

HLS run and Verilog simulate

cd hls/<module>
make

HLS run and Verilog simulate all

cd hls
make -f regress_Makefile

Design Checker run

cd hls/<module>
make cdc

Design Checker run all

cd hls
make -f regress_Makefile RUN_CDESIGN_CHECKER=1

Directory structure

Preprocessor Macro Definitions

Additional macros such as AUTO_PORT, FORCE_AUTO_PORT, CONNECTIONS_ACCURATE_SIM, CONNECTIONS_FAST_SIM, CONNECTIONS_SIM_ONLY, CONN_RAND_STALL, CONN_RAND_STALL_PRINT_DEBUG, CONNECTIONS_ASSERT_ON_QUERY, and DISABLE_PACER may be used in MatchLib. These macros are primarily defined, implemented, and documented in Connections. For more detail on these macros, see the Connections documentation.

Command-line Simulation Settings

Many of the flags above are design-specific, and so are typically codified into design Makefiles. However, some of the variables pertain to different simulation modes, and it is desirable to simulate the same design under different settings for different purposes. Accordingly, we provide the following command-line environment flags for use with the cmod or hls steps:

To accurately simulate expected RTL performance, use the default settings. For robust verification, simulate with four different modes: both SIM_MODE=1 and SIM_MODE=2, with random stalling both enabled and disabled and various random seeds.

Questions and Contributions

We welcome feedback and contributions from the open-source hardware community. If you have a question or problem, please file an issue on GitHub. To contribute bugfixes or new features, submit a pull request. For business inquiries, please contact researchinquiries@nvidia.com. For press and other inquiries, please contact Hector Marinez at hmarinez@nvidia.com.

Contributors

MatchLib originated as a project of NVIDIA Research.

Contributors to the initial open-source release (alphabetical): Jason Clemons, Christopher Fletcher, Davide Giri, Ben Keller, Brucek Khailany, Alicia Klinefelter, Evgeni Krimer, Hyoukjun Kwon, Ziyun Li, Michael Pellauer, Nathaniel Pinckney, Antonio Puglielli, Sophia Shao, Shreesha Srinath, Gopalakrishnan Srinivasan, Christopher Torng, Rangharajan Venkatesan, Sam Xi

Portions of MatchLib are derived from code in Mentor Graphics' Algorithmic C Datatypes v3.7.1 (also released under the Apache 2.0 license). See individual file headers for details.

MatchLib's back annotation feature is dependent on RapidJSON released under the MIT License.

Attribution

If used for research, please cite the DAC paper:

Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, and Brian Zimmer, "A modular digital VLSI flow for high-productivity SoC design," in Proceedings of the ACM/IEEE Design Automation Conference, June 2018.