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RVBS - RISC-V Bluespec SystemVerilog Specification

RVBS (pronounced "rubs") is an ISA level description of the RISC-V instruction set in Bluespec SystemVerilog. It uses the BID library to describe the instructions, providing a readable, executable and synthesizeable specification, with an AXI interface, that could be used as a golden model.

RVBS is not a heavily pipelined, superscalar or optimised RISC-V core. It is however capable to boot small embedded operating systems.

RVBS currently supports:

RVBS supports traps between privilege modes, but Supervisor mode is not fully implemented.

Building RVBS

In order to build a RVBS Bluesim simulator, you will need a valid installation of Bluespec SystemVerilog on your machine. RVBS relies on the following three Bluespec libraries:

BID is a submodule of the RVBS repository. Recipe, BitPat and BlueStuff are themselves submodules of the BID repository. In order to checkout all of them, you need to run:

$ git submodule update --init --recursive

Once the libraries are available, you can build RVBS and specify a number of build options as environment variables. The XLEN environment variable must be set to one of 32 or 64 to specify the XLEN to build with. The following optional environment variables are available:

Bluesim

Several Bluesim build targets are available:

The generated simulator is found under the output/ folder, and when run, will execute the program found in test-prog.hex.

Examples

$ make RVM=1 XLEN=64 MEM_SIZE=32768 sim
$ make RVC=1 rvfi-dii
$ make isa-test

Run time flags

The +itrace flag can be specified on the command line when running the simulator to get an instruction trace in stdout as follows:

$ output/rvbs-rv64IM +itrace

Verilog

To build a 32-bit verilog module with support for compressed instructions, you can run:

$ make RVC=1 XLEN=32 verilog

The generated verilog can be found in the output/rvbs-rv32IC-vdir/ folder. Specifically, the rvbs verilog module with an AXI4Lite interface can be found in output/rvbs-rv32IC-vdir/rvbs.v.

TODOs, upcoming features and experimentations...

References